PUBLIC BETA · FREE DOWNLOAD

Design thesignal chain.Deploy itto silicon.

NODE GRAPH · VIRTUAL SCOPES · CASPER TOOLFLOW · RFSoC

Apexia Fabric is a visual RF system design tool for AMD RFSoC platforms. Compose signal chains in a node-graph editor, watch sample rates and spectra propagate live, probe any point with virtual scopes; then hand the design to real hardware through the CASPER toolflow.
DOWNLOAD THE BETARELEASES ON GITHUB

BLOCK TYPES101

EXAMPLE DESIGNS7

HARDWARE NEEDEDNONE TO SIMULATE

EXPORTVIVADO TCL · casperfpga

PLATFORMSWINDOWS · MACOS · LINUX

FREE BETA · PRERELEASE SOFTWARE

Apexia.Fabric

LATTICE · PITCH 16 · IDLE
Apexia Fabric architecture view: a distributed three-node ZCU216 system with White Rabbit timing, component library, and live system inspector
FIG. 01 · ACTUAL APPLICATIONA distributed three-board coherent array with White Rabbit timing, gain budget and data rates computed live.
[ 01 ]

THE WORKFLOW

Design, simulate, deploy.

01 / 03[ NODE GRAPH ]

DESIGN

A node-graph editor with 101 block types across RF, DSP, timing, channelization, measurement, and system I/O. Sample rates, data types, and center frequencies propagate live through the graph; type-checked ports catch impossible chains before you build them.

02 / 03[ NO HARDWARE ]

SIMULATE

Probe any edge with virtual scopes: spectrum, time, constellation, waterfall, and beamformer views. The whole app runs in simulation with no hardware attached.

03 / 03[ CASPER ]

DEPLOY

Export Vivado TCL and casperfpga Python for the CASPER toolflow, connect live to real boards, configure RF data converters at runtime, and walk multi-tile synchronization with the built-in MTS wizard.

[ 02 ]

DSP LIBRARY

A working DSP vocabulary, built in.

A full library of DSP processing blocks, waveform presets, and seven complete example designs; the same processing vocabulary as our IP cores, in a tool you can explore before any hardware exists.
[ 03 ]

BOARD MODELS

Hardware truth built in.

Boards aren't icons; they're models. Converter counts, sample-rate limits, port and clocking configuration come from YAML board definitions, so the design that validates in Fabric is one the silicon can actually run.
FIG. 02 · BOARD PROPERTIES
Apexia Fabric board properties dialog showing ZCU216 specifications, port configuration, and clock/sync switches
SUPPORTED BOARDSYAML BOARD DEFINITIONS
[ 04 ]

DOWNLOAD

Download the latest Apexia Fabric Beta.

Apexia Fabric is prerelease software. It runs fully in simulation with no hardware attached; expect rough edges and rapid updates.

Apexia.Fabric

[ BETA ]LATEST RELEASE
01 / 03

Windows 10/11

Installer (.exe) · x64

SmartScreen may warn; click More info → Run anyway.

DOWNLOAD .EXE
02 / 03

macOS 12+

Disk image (.dmg) · Apple Silicon

First launch: right-click the app → Open → Open.

DOWNLOAD .DMG
03 / 03

Linux

AppImage + .deb · x64

chmod +x the AppImage, or sudo apt install ./<file>.deb.

DOWNLOAD APPIMAGE
[ SHA256 ]VERIFY YOUR DOWNLOAD

Every release ships a SHA256SUMS file. Check it with the command for your system.

LINUX
sha256sum -c SHA256SUMS
MACOS
shasum -a 256 -c
WINDOWS
CertUtil -hashfile <file> SHA256

Hardware: simulation works out of the box with nothing attached. Live capture with an ADALM-Pluto needs libiio. An attached BladeRF is detected automatically, and code generation works today for BladeRF, ADALM-Pluto, and LimeSDR.

SHIPS WITH EVERY APEXSDR

The softwarelayer ofApexSDR.

Every ApexSDR unit ships with Fabric; the same graph you simulate today is the instrument you deploy when the hardware arrives.
MEET APEXSDRQUESTIONS OR BUG REPORTS

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