PLATFORM FIELD GUIDE
Gen 1 RFSoC evaluation platform
ZCU111 field guide.
The ZCU111 is AMD's evaluation kit for the first-generation Zynq UltraScale+ RFSoC: eight 12-bit RF-ADCs at up to 4.096 GSPS and eight 14-bit RF-DACs at up to 6.554 GSPS beside a full UltraScale+ fabric. It is still a current AMD kit, with official PYNQ images and CASPER toolflow support. This guide covers what's on it, how Gen 1 differs from Gen 3, and where bring-up time actually goes.
AT A GLANCE
At a glance.
- DEVICE
- Zynq UltraScale+ RFSoC ZU28DR (Gen 1)
- RF-ADC
- 8 channels · 12-bit · 4.096 GSPS
- RF-DAC
- 8 channels · 14-bit · 6.554 GSPS
- RF INPUT RANGE
- 4 GHz full-power bandwidth (Gen 3: 6 GHz)
- CLOCKING
- On-board LMK04208 + three LMX2594
- RF I/O
- XM500 RFMC card · baluns + direct SMA pairs
- MEMORY
- 4 GB DDR4 on PS (SODIMM) · 4 GB DDR4 on PL
- HIGH-SPEED I/O
- 4 × SFP28 cages · FMC+ (12 GTY lanes)
ARCHITECTURE
Architecture in brief.
The ZU28DR pairs four dual RF-ADC tiles and two quad RF-DAC tiles with the family's UltraScale+ fabric and Arm processing system. Each converter has a 48-bit NCO, a complex mixer and hardened decimation or interpolation. What Gen 1 lacks is Gen 3's convenience layer: no ADC step attenuator, fixed DAC output-current modes, decimation only to 8x (Gen 3 reaches 40x), and no on-chip clock forwarding between tiles.
The kit's value is the plumbing around the device. An LMK04208 jitter cleaner feeds three LMX2594 synthesizers that clock the converter tiles, all programmed from the processing system through an I2C-to-SPI bridge. The XM500 card breaks the converters out to SMA, half through baluns and half as direct differential pairs. That plumbing is where most integration surprises live.
BRING-UP
Bring-up: where the time goes.
01
Clock tree before everything
The LMK04208 locks first, then the three LMX2594s, before the RF tiles will start. All four sit behind an I2C-to-SPI bridge on the PS I2C bus: leave PS I2C out of a custom design and they cannot be reached. PYNQ does this for you; a production bitstream must own it.
02
MTS is a frequency plan
MTS works on Gen 1, but SYSREF, sample rate and fabric clocks must agree: SYSREF stays under 10 MHz and divides every PL clock that samples it. The default 7.68 MHz SYSREF fits 1966.08 MSPS, not 4.096 GSPS. Re-run alignment on every initialization and check per-channel phase after each cold start.
03
Gen 1 analog edges
ADC full scale is about +1 dBm (1 Vpp differential, 100 Ω) with no on-chip attenuator, and full-power bandwidth stops at 4 GHz, so gain and filtering live in your front end. Half the XM500 channels have baluns (0 to 1 GHz or 1 to 4 GHz); the rest are direct differential pairs.
04
Getting data off the board
Eight ADCs at 4.096 GSPS put over 500 Gb/s of 16-bit samples into the fabric. Four SFP28 cages carry 100 Gb/s between them, and the PL DDR4 (about 21 GB/s) cannot absorb every channel at full rate either. Rate reduction or triggering in the PL decides what leaves; size that path first.
DEPLOYMENT
Deploying it.
The ZCU111 is an open evaluation board on a 12 V bench supply, and we do not build an enclosure for it. To run one unattended, plan airflow across the RFSoC, watch die temperature through the system monitor with every channel at full rate, and bring RF and SFP28 out to a panel so the board's connectors are not the strain relief.
BUILDING ON IT
Building on it.
Our DSP cores (DDC and decimation chains, polyphase channelizers, and MTS-aware coherent ingest) matter more on Gen 1: with hardened decimation stopping at 8x, rate reduction in the fabric is what fits eight channels through the SFP28 cages.
The ZCU111 is on the CASPER toolflow's RFSoC platform list. Our CASPER integration service covers bitstream generation, custom yellow blocks, and hybrid CASPER/Vivado flows, and the same bench handles Gen 1 bring-up and the move to Gen 3 hardware.
FROM THE BLOG
Further reading.
RFSoC BRING-UP AND DEPLOYMENT
Running aZCU111program?
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