APEXIA PRODUCTS
SOFTWARE · VERIFIED IP · HARDWARE · RESEARCH
APEXIA FABRICBETA
APEXSDREARLY ACCESS
DSP IP CORESLICENSABLE
RFSoC ENCLOSURESCOMING SOON
NEURORFIN DEVELOPMENT
PRODUCT INDEX · STATUS
PRODUCT PORTFOLIO
Apexia.Fabric
Visual RF system design for RFSoC with node-graph signal chains, virtual instruments, simulation, and implementation export.
TARGETRFSoC
SIGNAL CHAINSNODE GRAPH
VIRTUAL INSTRUMENTSINCLUDED
OUTPUTIMPLEMENTATION EXPORT
02 / 058-channel coherent wideband SDR with 100 MHz instantaneous bandwidth per channel, 40GbE, and multi-board expansion.
COHERENT RX
IBW / CHANNEL
RESOLUTION
Signal-denoising research with measured results on a seed-controlled, held-out synthetic test set.
Channelization, DDC, NCO/DDS, and MTS-aware ingest delivered with verification harnesses.
1U/2U rackmount enclosures for the ZCU216 and RFSoC 4x2 with thermal management and front-panel I/O.
DSP IP CORES
Wideband channelization core with configurable channel count, decimation ratio, and prototype filter design. Production-grade implementation with verification harness.
DDC chains with NCO-driven mixing, CIC plus FIR/FIR-halfband decimation stages, and bit-true Simulink reference for system-level verification.
High-spurious-free dynamic range numerically controlled oscillators and direct digital synthesis blocks. Dithered, tunable, and synthesis-portable.
Reference design for multi-tile, multi-channel coherent ingest with MTS sequencing, per-channel calibration hooks, and AXI4-Stream output to PL fabric or DDR4.
HARDWARE
[ COMING SOON ]2U RACKMOUNTFROM$2,500
Compatible with Xilinx ZCU216
Running this board? Read the Xilinx ZCU216 field guide
[ COMING SOON ]1U RACKMOUNTFROM$2,500
Compatible with RealDigital RFSoC 4x2
Running this board? Read the RealDigital RFSoC 4x2 field guide
SIGNAL-PROCESSING R&D
[ R&D STAGE ]IQ PROTOTYPE MODEL+11.3 dB
MEAN SNR IMPROVEMENT
NeuroRF is trained on synthetic signal-noise pairs and runs on the RF hardware you already own as host software today, with an FPGA IP core on the roadmap. On a held-out test set of QPSK and 8-PSK signals at 3 to 10 dB SNR, it delivers a measured mean SNR improvement of +11.3 dB with no meaningful phase distortion.
AT LOWEST INPUT SNR+9.4 dB
AT 10 dB INPUT SNR+13.7 dB
INPUT SNR3 to 10 dB
MODULATIONQPSK · 8-PSK
PHASE BIAS< 1°
On a 256-window held-out test set, QPSK and 8-PSK in AWGN at 3 to 10 dB input SNR, NeuroRF improves measured SNR by +9.4 dB at the lowest input levels, rising to +13.7 dB at 10 dB. Phase bias is under 1 degree.
Denoising as the front stage for modulation classification and recovery. The current prototype trains directly on complex IQ data; recovery performance is active R&D, and numbers will be published when they clear our own benchmarks.
Pure software/IP core solution that enhances existing RF infrastructure. No new antennas, amplifiers, or front-end modifications required.
The prototype denoises a 2,032-sample IQ window in 3.9 ms on a desktop CPU. Real-time inference on RFSoC programmable logic is the design target; hardware latency figures will be published when measured on silicon.
Measured figures: IQ prototype model, 256-window held-out synthetic test set (seed-controlled, no overlap with training data), QPSK and 8-PSK at 4 samples/symbol, AWGN channel at 3 to 10 dB SNR. SNR improvement computed as 10·log₁₀(P_signal / P_residual) over the symbol region. CPU latency measured at batch 1; not an FPGA figure.
CUSTOM SOLUTIONS
PALM BAY, FLORIDA · 28.0345° N 80.5887° W
CLARITY BEYOND THE NOISE