Engineering Insights
Working notes on FPGA signal processing, AI/ML for RF, RFSoC development, and radar systems — written from active program experience.
DSPJul 25, 20269 min read
Digital Down Conversion (DDC): A Practical Guide
How digital down conversion works — NCO mixing, CIC and FIR decimation, bit growth, aliasing, and when to use the RFSoC's hard DDC blocks versus fabric.
DDCDSPFPGA
Read articleDSPJul 25, 20269 min read
CFAR Detection: CA vs OS vs GO/SO, Explained
How CFAR detection works — cell averaging, guard cells, clutter edges, target masking, and choosing between CA, OS, and GO/SO variants on an FPGA.
CFARRadarDetection
Read articleFPGAApr 14, 20268 min read
FPGA vs GPU for Real-Time Signal Processing
Discover why FPGAs deliver deterministic sub-microsecond latency for real-time DSP while GPUs excel at batch throughput. Learn when to choose each platform.
FPGAGPUSignal Processing
Read articleRF SystemsApr 10, 202612 min read
AESA Phased Array Beamforming on FPGAs
Phased array beamforming for AESA radar — array factor physics, beam steering, sidelobe control, and grating lobe avoidance, from theory to FPGA.
Phased ArrayBeamformingAESA
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