Own the systemconstraint, nota work package.

Move an RFSoC platform from board-on-the-bench to coherent IQ with one team owning clocking, RFDC tile configuration, MTS alignment, and cross-domain debug.

IN SCOPE

• LMK04208 / LMK04828 clock tree design and lock sequencing
• RF-ADC / RF-DAC tile configuration and calibration
• Multi-Tile Synchronization (MTS) bring-up across ZCU111, ZCU208, ZCU216, RFSoC 4x2
• Reference distribution and per-element sync verification
• Cross-domain debug across RF, fabric, and host-side capture

A productized 2 to 4 week fixed-firm-price engagement for teams evaluating direct-RF sampling receiver architectures. Delivered as a written architecture trade study with quantization analysis, performance bounds, and a defensible recommendation.

IN SCOPE

• Direct-RF vs. IF down-conversion tradeoff analysis
• Quantization, BER, MDS, and ROC modeling
• Multi-channel digitization architecture comparison
• Platform recommendation across the RFSoC family
• Written deliverable for PDR / CDR review packages

Independent review for phase-coherent multi-channel architectures, designed to expose calibration, timing, and interface assumptions before they become a board respin or critical test failure.

IN SCOPE

• MTS architecture and reference distribution review
• Per-element calibration approach assessment
• Phase-coherence budget across RF, ADC, and PL fabric
• Latency-deterministic pipeline review
• Written findings with severity-ranked recommendations

Production-grade DSP cores and digital beamforming pipelines for wideband signal chains. Fixed-point VHDL and Simulink/Model Composer cores built for latency-deterministic real-time operation.

IN SCOPE

• Polyphase channelization and digital down-conversion
• NCO/DDS and decimation chain development
• Digital beamforming subsystem development
• Fixed-point quantization and bit-true verification
• Simulink / Model Composer core development

CUDA-based post-processing servers that take IQ off the wire and turn it into usable data products. Built for sustained gigabit-class ingest, processing, telemetry, and archival.

IN SCOPE

• High-rate ingest and parsing pipelines
• GPU-accelerated correlation and data fusion
• System health monitoring and telemetry
• Sustained-rate IQ archival to disk and remote storage
• Satellite-uplink optimized data movement

Rapid prototyping of digital receivers and DSP pipelines using the CASPER toolflow on Xilinx RFSoC platforms. Production-style verification on a research timeline.

IN SCOPE

• CASPER bitstream generation targeting ZCU216 and ZCU111
• Custom Simulink yellow-block development
• tcpborphserver control paths and Python host tooling
• Hybrid CASPER + native Vivado / Vitis flows
• Bitstream verification and lab-floor bring-up

SDR-based detection and direction-finding systems for RF emitters, including coherent multi-channel receivers, real-time processing, and field-demonstrable prototypes.

IN SCOPE

• Multi-channel coherent SDR receiver architectures
• Real-time emitter detection and classification pipelines
• Direction finding and bearing estimation
• Rapid prototyping and live field demonstration
• Synthetic training-data pipelines for detection models

Multi-layer RF and mixed-signal hardware carried through signal-integrity and EMI/EMC validation, with qualification constraints considered from the first schematic.

IN SCOPE

• Multi-layer and RF front-end PCB design
• High-speed data-acquisition layout
• Electromagnetic simulation and modeling
• Signal-integrity and EMI/EMC validation
• DO-254 and MIL-STD design practices

Enclosure and structural design with full GD&T, rapid prototyping, thermal analysis, and environmental qualification planning for RF hardware.

IN SCOPE

• Enclosure and structural design with full GD&T
• Additive and subtractive rapid prototyping
• Thermal and structural analysis
• Environmental qualification to MIL-STD-810 / -1540E
• TRL maturation planning and test campaigns

Deep-learning detection and denoising for noise-dominated regimes, backed by GPU/HPC compute, synthetic-data pipelines, and explicit held-out evaluation.

IN SCOPE

• Deep-learning architectures for detection in noise
• Synthetic training-data generation pipelines
• GPU / HPC training and real-time inference
• Modeling and simulation of RF signal chains
• Seed-controlled, held-out benchmark methodology